As is well known in the prior art, an I2C (Inter-IC) bus is a bi-directional two-wire serial bus that provides a communication link between devices connected to the bus. Devices are typically considered as masters or slaves when data transfers are being performed. The master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.
FIG. 1 illustrates the prior art, 7-bit protocol used in I2C bus communications. This protocol is fairly simple, with a five-part format comprising: 1) A start bit 102 to initiate a transaction, 2) an address byte, with seven bits 104 denoting the address of the slave device and the eighth bit 106 denoting a read or write command, 3) data bytes 108, 4) an acknowledge bit 110 following each 8-bit address or data byte, and 5) a stop bit 112 to terminate the transaction.
Not illustrated in FIG. 1 is another, prior art protocol that uses a 10-bit addressing protocol in which the slave address 104 has the format 11110XX (as before, the eighth bit of this information byte is a read/write indicator 106). The five high order bits indicate that 10-bit addressing protocol is being employed, while the remaining two bits are the two high order bits of the slave address. The remaining 8 bits of the 10-bit address are then provided in the first data byte 108.
Both these 7-bit and 10-bit prior art addressing protocols permit an additional data byte 108 to contain additional addressing information, such as an internal register address of the slave device.
Although widely used, the I2C bus suffers from several drawbacks, one of which is the limited addressability/time inefficiencies inherent in its protocol. Prior art attempts at remedying this problem have chiefly involved adding external pins to the slave device. While this method does permit the I2C master to control a larger word addressing space, it requires larger package pin counts for any I2C slave devices to be so addressed.
The current invention provides access to a large address space without requiring additional external pins on the device addressed. Further, the invention provides an interface that is efficient for high priority accesses.